DK-DEV-5SGXEA7N【PDF 52/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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3-10

Accumulator and Chainout Adder

SV51004

2013.05.06

? Two 18 x 18 multipliers

? Three 9 x 9 multipliers

Related Information

Operational Mode Descriptions on page 3-11

Provides more information about the operational modes of the multipliers.

Accumulator and Chainout Adder

The Stratix V variable precision DSP block supports a 64-bit accumulator and a 64-bit adder.

For Stratix V devices, you can use the 64-bit adder as full adder.

The following signals can dynamically control the function of the accumulator:

? NEGATE

? LOADCONST

? ACCUMULATE

Table 3-3: Accumulator Functions and Dynamic Control Signals for 64-Bit Accumulator in Stratix V Devices

Function

Zeroing

Description

Disables the

accumulator.

NEGATE

0

LOADCONST

0

ACCUMULATE

0

Loads an initial value

to the accumulator.

Only one bit of the

64-bit preload value

Preload

can be “ 1 ” . It can be

0

1

0

used as rounding the

DSP result to any

position of the 64-bit

result.

Adds the current

Accumulation

result to the previous

0

0

1

accumulate result.

This function takes

the current result,

Decimation

converts it into two ’ s

complement, and adds

1

0

1

it to the previous

result.

Systolic Registers

There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not

configured in systolic FIR mode, both systolic registers are bypassed.

The first systolic register has two 18-bit registers that are used to register the upper multiplier ’ s two 18-bit

inputs. You must clock these registers with the same clock source as the output register bank.

Altera Corporation

Variable Precision DSP Blocks in Stratix V Devices

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